Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods and structures for using improved standard cells improved cell routability for manufacturing semiconductor devices.
Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another.
In this manner, integrated circuit chips may be fabricated. In some cases, integrated circuit or chips may comprise various devices that work together based upon a hard-coded program. For example, application-specific integrated circuit (ASIC) chips may use a hard-coded program for various operations, e.g., boot up and configuration processes. The program code, in the form of binary data, is hard-coded into the integrated circuit chips.
When designing a layout of various devices with an integrated circuits (e.g., CMOS logic architecture), designers often select pre-designed functional cells comprising various features (e.g., diffusion regions, transistors, metal lines, vias, etc.) and place them strategically to provide an active area of an integrated circuit. One challenge of designing a layout is accommodating ever-increasing density of cell components and still maintain routability for connecting various components of the cells. This is increasingly a challenge as dimensions of these components get smaller, such as for 10 nm or lower integrated circuit designs.
FIG. 1 illustrates a typical standard cell for a 10 nm node design. A cell 100 comprises a plurality of Metal-2 (M2) routing tracks 140. The cell 100 is an example of a 9-track cell, which may comprise a plurality of components that densely populate the cell. The cell 100 comprises six metal pins (130a-130f) (e.g., Metal-1 (M1) metal pins). The six metal pins 130a-130f are input pins. The cell 100 also includes an output “U-shaped” pin 120. The cell 100 includes a VDD metal connection on one routing track 140, and a VSS metal connection on another routing track 140.
As shown in FIG. 1, metal pins 130b-130f are required to be connected using only two routing tracks 140. Metal pin 130a may be connected using three routing tracks. As such, three metal tracks 140 have to be used to connect all six input pins 130a-130f. In light of the VDD line 150, the VSS line 160, the output pin 120, the utilization of three M2 tracks 140 to connect the six input pins 130a-130f can cause the cell 100 to become very difficult to connect. This causes routing-congestion and causes the routing task to be more difficult.
In order to alleviate some of the routing concerns, designers have turned to manually placing M2 pins in cell design. Manually placed M2 pins can be optimized to maximize pin accessibility that cannot be done by design automation tool (router) because the automation tool need be implemented on the full chip scale, and thus, cannot properly perform thorough optimization.
Turning now to FIGS. 2 and 3, FIGS. 2 illustrates a typical cell without horizontal M2 pins, wherein FIG. 3 illustrates a typical cell comprising horizontal M2 pins. FIG. 2 illustrates a cell 200 that comprises a layout without horizontal M2 pins. The cell 200 includes a plurality of vertical M1 pins. The cell 200 includes six input M1 pins (230a-230f), and an output pin 220. The cell 200 also includes a plurality of vertical semiconductor formations 270, e.g., gate formations for a transistor. The cell 200 also includes a plurality of horizontal metal tracks 240. At boundary of the cell 200, on a metal VDD line 250 and a metal VSS line 260 are defined.
FIG. 3 illustrates a cell 300, on which horizontal M2 pins are manually placed and optimized. A plurality of horizontal M2 metal pins (375a-375c) may be manually defined onto the cell 300. Manually adding the M2 horizontal metal formations provides for extending pin accessibility. Some of the M2 pins (375b, 375c) are generally not continuous lines, wherein 375b and/or 375c may represent a plurality of non-continuous M2 horizontal metal formations. The fact that some of the M2 pins (375b, 375c) are generally not continuous lines can make it difficult or substantially impossible for an automated router to process the design.
FIG. 4 shows the DRC error results of the routing experiment for the function cell 200 and 300 as shown in FIG. 2 and FIG. 3 respectively. The DRC errors may include spacing error, pin width errors, and/or enclosure errors. Using electronic design automation (EDA) router tools to implement automated horizontal pin for the function cell 200, which leads to congestion and difficulties in routing, a large number of DRC errors results. As shown in FIG. 4, using manually added horizontal pins for the function cell 300, the routing efficiency is significantly improved and a much lower number of DRC errors result. One common problem associated with manually drawn horizontal M2 pins is that it is not possible to optimize the horizontal M2 pin design toward the M3 route track. This is so because the M3 route track is not fixed in relation to the cell boundary, and its actual shift relative to the cell boundary after cell placement cannot be predicted during the cell design phase.
Turning now to FIGS. 5 and 6, FIG. 5 illustrates a stylized depiction of a cell showing a post-placement M3 route track with zero shift relative to the cell boundary, while FIG. 6 illustrates a stylized depiction of a cell showing a post-placement M3 route track with a 32 nm shift relative to the cell boundary. Both cells have the exact same design and function and show different M3 route track shift because they are placed in different locations in the circuit layout. The cells of FIGS. 5 and 6 may be a 10 nm cell containing a poly pitch of 64 nm and a metal pitch (M1, M2, M3) of 48 nm. FIG. 5 illustrates a cell 500 that comprises a plurality of M3 tracks 510. As shown in FIG. 5, the M3 tracks are spaced exactly a pitch width from the cell boundary, thus a zero shift. FIG. 6 illustrates a cell 600 that comprises a plurality of M3 tracks 510. As shown in FIG. 6, the M3 tracks are not spaced exactly a pitch width from the cell boundary, but is shifted by 32 nm from the cell boundary, thus a 32 nm shift.
Generally, the M2 route tracks in conventional standard cells are fixed relative to the cell boundary, while the M1 pins are generally optimized toward the M2 route track to maximize pin accessibility. In conventional standard cells that have horizontal M2 pins, one problem is that the M3 route tracks are not fixed or anchored to the cell boundary, as indicated in FIG. 6. This mismatch is generally caused by a mismatch between the poly-pitch (64 nm) and the M3 pitch (48 nm). As such, it is substantially impossible to optimize any manually drawn M2 pin relative to the M3 route track. This is yet another problem associated with manually drawing M2 pins for overcoming routing problems in a congested cell.
One problem associated the M3 shift described above is a possibility of poor accessibility to features formed due to the shift (e.g., 32 nm) described above. Turning now to FIGS. 7 and 8, FIG. 7 illustrates a stylized depiction of a cell showing a pin access relative to an M3 route track with zero shift relative to the cell boundary, while FIG. 8 illustrates a stylized depiction of a cell showing a pin access relative to an M3 route track with a 32 nm shift relative to the cell boundary.
FIG. 7 illustrates a functional cell 700 that comprises a plurality of vertical M3 route tracks 740. The cell 700 also comprises a first integrated circuit feature 710 (e.g., M2 horizontal pin), a second integrated circuit feature 720, and an integrated third circuit feature 730. The features 710-730 (e.g., M2 horizontal pins) are positioned over the M3 routing tracks in such a manner that a maximum number of pin access points can be used to gain access to the M3 metal layer. Accordingly, three pin access points 712, 714, 716 can potentially be utilized by M3 route to connect to the feature 710. In the route technology, more pin access points will provide better routing efficiency and routing density. The three pin access point 722, 724, 726 can potentially be utilized by M3 route to connect to the feature 720. The two pin access points 732, 734 can potentially be utilized by M3 route to connect to the feature 730.
As shown in FIG. 8, a shift in the M3 routing track could cause a reduction in the number of pin accesses that can be provided to the features 710-730. FIG. 8 illustrates a functional cell 800 that comprises a plurality of vertical M3 route tracks 840. FIG. 8 shows a cell 800 that comprises the features and the corresponding pin access points similar to the description in the context for FIG. 7 above.
The cell 800 comprises a first integrated circuit feature 810, a second integrated circuit feature 820, and an integrated third circuit feature 830. The M3 routing tracks 840 are shifted by about 32 nn. This shift may be the result of a mismatch between the M3 pitch (e.g., 48 nm) and the poly-pitch (e.g., 64 nm) of the cell 800. The features 810-830 (e.g., M2 horizontal pins) are positioned over the M3 routing tracks in such a manner that a maximum number of pin access points can be used to gain access to the M3 metal layer at zero shift of M3 track to the cell boundary. However, due to the shift between the M3 routing track 840 and the cell boundary, less than optimum number of pin access points can be provided on the features 810-830. For example, due to the shift, only two pin access points (814, 816) can be formed on the feature 810, providing a 2-pin access. As a result of the shift, only two pin access points (824, 826) can be provided on the feature 820, providing only a 2-pin access. Further, due to the shift, only a single pin access point 834 can be provided on the feature 830, providing only a 1-pin access. Therefore, the same horizontal pin design implemented into a cell (FIG. 7) that provides sufficient pin accessibility in a zero-shift cell is compromised and results in poor pin accessibility in a cell (FIG. 8) that has a 32 nm M3 route track shift. Because of the shift described above, there is less access to metal lines, which may cause routing problems, Thus, there are limited resources for connect to other cells due to the congestion. Therefore, as described above, there are various inefficiencies, errors, and other problems associated with the state-of-art.
The present disclosure may address and/or at least reduce one or more of the problems identified above.